- Enables continuous-time digital calibration of delta-sigma AD converter
- This is achieved using a multi-rate LMS algorithm
As advanced driver assistance systems (ADAS) and self-driving vehicles are gradually becoming a reality, an increasing need can be seen for automobiles that incorporate a variety of sensors, such as millimetre wave radar, LiDAR, and ultrasonic wave sensors for detecting objects and people, and also create an awareness of the vehicle’s surroundings.
AD converters used to convert analogue signals from such sensors into digital signals at a high speed and precision. However, the harsh automotive vehicle conditions have made it difficult to obtain stable performances.
In response, Renesas Electronics in collaboration with Hitachi, has developed a technology that will enable continuous-time digital calibration of a delta-sigma (ΔΣ) modulator and an analogue-to-digital (AD) converter circuit. This will make high-speed, high-precision ΔΣ AD converters capable of withstanding rough conditions.
LMS algorithm to measure and calibrate the transfer function of a continuous time ΔΣ modulator
Generally, RC integrators that do not require an input sampling capacitor and deemed suitable for high bandwidth, are employed for increasing the conversion speed of the ΔΣ AD converter. These integrators are connected in cascade for a high-order loop filter. However, when the input is excessively large, precision is lost due to the ΔΣ modulators’ oscillation. On the other hand, a multi-stage ΔΣ modulator consisting of low-order ΔΣ modulators connected in multiple stages can be used to achieve a higher-order ΔΣ modulator while maintaining the stability of the ΔΣ AD converter. However, in a multi-stage configuration, precision suffers if the analogue transfer functions and digital transfer functions do not match perfectly, and for this reason such configurations are susceptible to environmental variations such as changes in temperature, making it difficult to achieve higher precision.
To solve the difficulty in achieving higher precision, typical of multi-stage ΔΣ modulators, which are extremely stable, the new technology digitally calibrates the transfer function of the ΔΣ modulator. This technology inputs a pseudo-random number signal to the quantizer-input of the first-stage ΔΣ modulator as a reference signal, which makes background search possible using an LMS algorithm of the first-stage modulator’s noise transfer function and the second-stage modulator’s signal transfer function at the same time. The coefficients searched by the LMS algorithm are input to FIR digital filters, and the second-stage modulator result is used to completely cancel the quantisation error of the first-stage modulator, making it possible to obtain high-precision AD conversion results. This new technology enables calibration within the digital circuits operating in the background even if the characteristics of the analogue integrators are affected by environmental variations such as temperature changes. As a result, high precision and robustness in a highly stable multi-stage ΔΣ modulator was successfully achieved, something previously considered difficult if not impossible.
Multi-rate LMS search algorithm that enables smaller circuit scale and low power consumption
When searching ΔΣ modulator transfer functions using the LMS-based coefficient search algorithm, the number of tap coefficients required by the FIR digital filter was very large (more than 100) when the gain-bandwidth product of the integrator amplifier circuit was insufficient, which meant that the scale of the logic circuits would be impracticably large. However, it was found that extracting only the transfer function characteristics near the signal bandwidth was sufficient for transfer function calibration.
So, by reducing unnecessary frequency information by means of a post-conditioner, it became possible to substantially reduce the number of tap coefficients, even when the gain-bandwidth product of the amplifier circuit was small. In addition, by using shift registers to store reference signal data, Renesas and Hitachi developed a new calibration circuit using an LMS algorithm that was not affected by sub-sampling. This made it possible to reduce the operating frequencies of the coefficient search and FIR filter to one-fourth what they previously were. The world’s first digital calibration circuit technology successfully reduced the circuit scale while also reducing power consumption.
Reduced operating frequency
Previously, digital calibration circuits were required to operate at an oversampling frequency of AD converters, but the new circuit reduces the operating frequency to one-fourth the previous frequency. As a result, high-speed, high-precision operation with a 15 MHz signal bandwidth and 74.3 dB dynamic range is achieved when operating at an oversampling frequency of 480MHz. By reducing the digital calibration circuit operating frequency to 120MHz, a low-power operation is also achieved, with 37mW power consumption (analogue:19mW, digital:18mW).
In addition, the new, robust technology provides stable performance over a wide temperature range of −20 to 125 degrees Celsius, making it capable of stable operation under rough conditions.
Renesas will continue to develop practical applications for this technology to enable high-speed, high-precision, and highly reliable AD conversion of automotive sensor signals in order to accelerate the widespread adoption of self-driving technology and the realisation of safer and more secure driving experience.