PTP Timestamping For Data Centre and 5G Infrastructure By Marvell


Dual 400GbE MACsec PHY for leading Optical PHY and SerDes Technology

Hardware-based point-to-point encryption comprising Ethernet speeds of up to 400G is being deployed in cloud, carrier and enterprise networks to address the market demand for enhanced data security. Additionally, stringent timing requirements of 5G radios should be able to meet the timing accuracy that is needed to be delivered by networks for supporting these 5G services.

Accordingly, Marvell, a provider of semiconductor solutions, introduces its dual 400GbE (Gigabit Ethernet) MACsec PHY transceiver with 256-bit encryption and Class C compliant precision time protocol (PTP) timestamping, for enabling high performance, security and transfer speeds to next-generation of 5G networking.

Incorporating accuracy


The new 400GbE PHY device incorporates Marvell’s 56G PAM4 SerDes technology, IEEE 802.1AE 256-bit MACsec encryption and highly accurate PTP timestamping. This comprehensive and innovative feature set enables network equipment manufacturers to deliver solutions with increased throughput, enhanced security and better timing precision for data centres, enterprises and 5G infrastructure applications.

Better compatibility

The 88X7121P, the latest addition to Marvell’s Alaska C family of Ethernet transceivers, supports both re-timing and transmission applications and is footprint and software-compatible to Marvell’s 88X7120 PHY, providing design flexibility for customers. The new device is fully compliant to IEEE standards for 400GbE, 100GbE and 50GbE and exceeds the electrical specifications to interface with QSFP-DD and OSFP optical modules.

The 88X7121P’s 256-bit MACsec-based encryption for point to point links provides enhanced security and allows for flexible deployment of MACsec encryption without incurring cost and power burden of including this functionality in the switch ASIC. Highly accurate Class C PTP timestamping incorporated in the device enables enhanced timing precision required for carrier, wireless backhaul and 5G infrastructure applications.

High Linearity I/Q Demodulator Supports 1GHz Bandwidth

Supporting dedicated devices

Data centres require new technologies to support dedicated devices in infrastructure and usher in a new era of connected intelligence and edge computing. By providing support for all Ethernet speeds from 1GbE to 400GbE, Marvell’s dual 400G MACsec PHY, the 88X7121P, in combination with Marvell’s Prestera CX 8500 400GbE switch, allows data to be securely moved to the smart edge to meet the bandwidth and latency demands for critical 5G and AI applications.

“The launch of our dual 400GbE MACsec PHY integrating our industry-leading 56G PAM4 SerDes solution in advanced FinFET process extends our leadership in both high-speed Ethernet PHYs and high-speed SerDes technology,” said Faraj Aalaei, executive vice president of the Networking Business Group at Marvell Semiconductor, Inc. “Marvell’s new PHY is optimized for differentiated, innovative solution deployments to address the distinctive security and performance requirements of hyper-scale data centres, enterprise networks and 5G infrastructure.”

“We see an uptrend in data centres transitioning to 100GbE, 200GbE and 400GbE to meet ever-increasing processing and me/O bandwidth demands, particularly as artificial intelligence and machine learning workloads ramp. Enhanced protection and security of data are also becoming a key requirement for cloud operators and network-equipment vendors,” said Bob Wheeler, principal analyst for networking at The Linley Group. “Marvell’s new 400GbE PHY addresses the imperative requirement of enhanced MACsec security for data-centre interconnects while offering the proven high-speed data performance that network-equipment vendors demand.”



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