This Design Can Be Used For Making Efficient Transceiver Systems



This reference design can be used in the development of an efficient Software Defined Radio(SDR) System

The AD9361 is a high performance, highly integrated radio frequency (RF) Agile transceiver. It is designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. This reference design is based on the design and development of an isolated signal and power transceiver using AD9361.

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Configurable digital interface


The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers. It simplifies the in-design by providing a configurable digital interface to a processor. The AD9361 receiver LO operates at a frequency ranging from 70 MHz up to 6.0 GHz. The transmitter LO operates for frequency ranging from 47 MHz up to 6.0 GHz. This range covers most licensed and unlicensed bands. Additionally, it supports channels having bandwidths less than 200 kHz to 56 MHz.

Shares a common frequency synthesizer

The receiver section contains all blocks necessary to receive RF signals and convert them to digital data that is usable by a BBP. Two independently controlled channels can receive signals from different sources, allowing the device to be used in multiple-input, multiple-output (MIMO) systems while sharing a common frequency synthesizer.

Customisable front-end receiver

Each channel has three inputs that can be multiplexed to the signal chain. This makes the AD9361 suitable for use in diversity systems with multiple antenna inputs. The receiver is a direct conversion system that contains a low noise amplifier (LNA). It is followed by matched in-phase (I) and quadrature (Q) amplifiers, mixers, and band shaping filters. It converts received signals to baseband for digitization. External LNAs can also be interfaced to the device. This interface can allow designers the flexibility to customize the receiver front end for their specific application.

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Shares common frequency synthesizers

The transmitter section consists of two identical and independently controlled channels. It provides the processor with all digital processing, mixed-signal, and RF blocks. These processes are necessary to implement a direct conversion system while sharing a common frequency synthesizer. The digital data received from the BBP passes through a fully programmable 128-tap FIR filter with interpolation options. The FIR output is sent to a series of interpolation filters. These filters provide additional filtering and data rate interpolation before reaching the DAC.

Adjustable sampling rate

Each 12-bit DAC has an adjustable sampling rate. Both the I and Q channels are fed to the RF block for upconversion. When converted to baseband analogue signals, the I and Q signals are filtered to remove sampling artefacts. It is then fed to the upconversion mixers. At this point, the I and Q signals are recombined and modulated on the carrier frequency for transmission to the output stage.

Offers a wide range for noise adjustments

The combined signal also passes through analogue filters. It provides additional band shaping. The signal is then transmitted to the output amplifier. Each transmit channel provides a wide attenuation adjustment range with fine granularity. It helps designers in optimizing the signal-to-noise ratio (SNR).

Uses parallel data ports for data transfer

The AD9361 operates using a reference clock. It can be provided by two different sources. The first option is to use a dedicated crystal with a frequency between 19 MHz and 50 MHz. It is connected between the XTALP and XTALN pins. The second option is to connect an external oscillator or clock distribution device (such as the AD9548) to the XTALN pin (with the XTALP pin remaining unconnected). If an external oscillator is used, the frequency can vary between 10 MHz and 80 MHz.

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The AD9361 data interface uses parallel data ports (P0 and P1) to transfer data between the device and the BBP. The data ports can be configured in either single-ended CMOS format or differential LVDS format. Both formats can be configured in multiple arrangements. It matches system requirements for data ordering and data port connections.

These arrangements include a single-port data bus, dual-port data bus, single data rate, double data rate, and various combinations of data order. It is used to transmit data from different channels across the bus at appropriate times.

Hardware handshake signalling

Bus transfers are controlled using simple hardware handshake signalling. The two ports can be operated in either bidirectional (TDD) mode or full-duplex (FDD) mode. In FDD mode, half the bits are used for transmitting data and half are used for receiving data. This interface can also be configured to use only one of the data ports for applications that do not require high data rates. These applications generally use fewer interface pins.

All the designs and documents are available in the Analog Devices website. The device can be used in many applications including point to point communication systems, Femtocell /picocell/microcell base stations and general-purpose radio systems features.





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