New NVRAM Saves Power Over DRAM And Flash Memory

-Manas

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  • According to the research, the floating gate of carriers (nominally setting the device to ‘logic 1’ state) takes 3ns to obtain a full discharge state
  • This newly designed memory device does not need the reconstructive write that is necessary after reading a ‘1’ from DRAM

The University of Lancaster recently published details regarding its newly researched non-volatile memory(NVRAM). It can be written and erased for one-hundredth of the energy needed by flash or DRAM. It is also fast enough to be used instead of DRAM.

This tiny amount of energy was discovered last year. The structure has now been refined to allow flash-like readout simplicity. It has been simulated in sufficient depth. It predicts good behaviour and suggests suitable write, erase and read strategies for arrays.

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The memory cell of the memory is much like flash memory. It uses a floating gate to store the memory state. The isolation for the gate of the device is near to perfect isolation. It is recorded to be 2V. The is the voltage that is needed to breach it for programming. It is required due to the dual quantum well resonant tunnelling junction (made from alternating layers of AlSb and InAs). This junction is created between the floating gate and the control gate.

Professor Manus Hayne, who is leading the research in a recent interview said,

“ The channel exploits the unusual band alignment of In(Ga)As and GaSb, where the conduction band of InAs is below the valence band of GaSb. This means that, even in the absence of doping, electrons will flow from the full valence band of the GaSb into the conduction band of the InAs channel.

This was the case before, but here we have made the In(Ga)As channel narrow so that confinement pushes the energy of the channel state up to just above the GaSb valence band, such that it is unoccupied and normally-off unless a suitable voltage is applied. This allows a readout that is similar to flash and should deliver far superior 1-0 contrast to our previous devices allowing them to be connected in a fully-addressable array.

A patent for this device has been applied for. MSB has revealed the tunnelling current flow as well as modelling the confined states for different voltages. Simulating the gate programming resonant tunnelling junction using Nextnano. Another Nextnano product, nextnano++, was also used.

The current flow can then be fed into the SPICE model of the device, and nextnano++ used to simulate the read. The very low level of disruption to neighbouring bits is seen as a result of the new model calculating the current flow, and the fact that the resonant tunnelling has a very sharp onset with applied voltage. Another important aspect is that because we can model the current flow, we can also model the write/erase speed, and it is fast. ”

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According to the research, the floating gate of carriers (nominally setting the device to ‘logic 1’ state) takes 3ns to obtain a full discharge state. The charging time for the device is 5ns. The local memory disruption is low enough for the transistors to be used in analogous arrangements. It can be used for NAND and NOR flash memories.

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According to the team, the write and erase process can work in a low-power consuming process. The major area of concern is the amount of power needed to read the data. Read can be low energy consuming task but it depends on how little source-drain current can be reliably detected.

This newly designed memory device does not need the reconstructive write that is necessary after reading a ‘1’ from DRAM. It is also independent of DRAM’s periodic refresh. Equipped with all these features, this new memory product can be a new innovation in the DRAM industry.


 

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