Enhance AI-Based Vehicle Controls Using This Hardware Engine


  • 99 per cent of current NNs execute within the aiWare3P core without any host CPU intervention
  • The aiWare3P delivers NN acceleration for L2-L3 automotive AI-based systems

AImotive has introduced its latest release of aiWare3 NN (Neural Network) hardware engine. According to the company, this new design is incorporated with a range of new features. These features can optimise and improve the performance and power consumption of the device. The design features an enhanced host CPU offload combined with a simpler layout for larger chip designs.

AI based algorithm
AI-based algorithm


Based on multi-core and multichip design

Each aiWare3P hardware IP core is said to offer up to 16 TMAC per second(>32 TOPS) at 2GHz. The hardware is implemented on a multi-core and multi-chip design. It is capable of delivering up to 50+ TMAC per second (>100 INT8 TOPS). Hence, it makes it ideal for multi-camera or heterogeneous sensor-rich applications.


The core of the hardware is designed according to the AEC-Q100 standards. This core makes the hardware resistive towards extended temperature operation. It also includes a range of features that enable users to achieve ASIL-B and above level certifications.

Extends the range of supporting hardware

It produces higher efficiency for a wide range of neural network functions. This is due to the improved on-chip data reuse and implementation of more sophisticated scheduling algorithms. The company has also upgraded its external memory bandwidth management. By this upgrade, it can now support a larger portfolio of pre-optimised embedded activation and pooling functions.

Runs on a real-time data compression method

It supports real-time data compression. This method reduces the requirements of external memory bandwidth for large networks. It creates cross-coupling between C-LAM convolution engines and F-LAM function engines. This, as a result, increases the execution efficiency of the system.

Gesture Control Empowered By Low Power Motion Detecting Sensor Chip

Based on the logical tile-based data management system

aiWare3P is based on a physical tile-based microarchitecture. It enables the physical implementation of large aiWare cores. It does so by minimizing the timing constraints on any process node. The hardware features logical tile-based data management. It enables efficient workload scalability up to a maximum of 16 TMAC/s per core. It eliminates the need for caches, NOCs or other complex multi-core processors-based approaches.

Marton Feher, senior vice president of hardware engineering for AImotive recently said in an interview,

Our production-ready aiWare3P release brings together everything we know about accelerating neural networks for vision-based automotive AI inference applications. We now have one of the automotive industry’s most efficient and compelling NN acceleration solutions for volume production L2/L2+/L3 AI. When complemented by AImotive’s significant algorithmic, safety and production expertise for automated driving, we believe we offer our customers the most technology-rich automotive-focused solutions available today”.

Targets heterogeneous sensor applications

The aiWare3P hardware IP is being deployed in a range of L2/L2+ production solutions. These softwares are also being adopted for studies of more advanced heterogeneous sensor applications.

The company also informed that their upcoming products will devices which can bear high-resolution inputs in order to exceed public benchmarks. The aiWare3P RTL will be in stock for all customers by January 2020.




Please enter your comment!
Please enter your name here

Are you human? *