This RISC-V based Core Design Can Boost Micro-controller Features

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  • Western Digital has recently introduced two new processor cores featuring compact size and high-performance 
  • Company has also released the source code of their register-transfer level (RTL) design and technology

Today, if you want to build a high-performance computing device, you may find all the software you need in a free or open form. The same is not true with the processor chips that run those free software. Generally, these processor chips are patented technologies designed with some particular configurations.

RISC-V is an open ISA(Instruction set architecture) that enables a new era of processor innovation. To further accelerate RISC-V processing architectures, Western Digital has contributed hardware and software solutions to grow a RISC-V ecosystem.

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Western Digital has recently introduced two new processor cores featuring compact size and high performance. The SweRV Core EH2 and the SweRV Core EL2 has been introduced in the SweRV portfolio of microcontroller CPUs.Both of these chips are based on RISC-V architecture.

The performance factor of up to 6.3 CoreMark per MHz

According to the company, Core EH2 is a 32-bit in-order core designed for use in microcontrollers. It uses a 2-way superscalar design. It is equipped with a nine-stage pipeline and a two-way simultaneous multithreading capability. The EH2 is a performance-enhanced version of the EH1. EH1 was introduced last year and supported surface mount technology(SMT). It is fabricated using TSMC’s 16 nm FinFET fabrication technology. This technology helps in increasing the efficiency of the processor in terms of power, performance and area.

The EH2 core is said to deliver a performance factor of up to 6.3 CoreMark per MHz. This factor is based on the simulations done by Western Digital. The SweRV Core EH2 can be used for the same applications as its predecessor. With the current configurations, EH2 core can work beyond its previous applications and can tend towards more complex processing systems.

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Features a one-way scalar design

SweRV Core EL2, on the other hand, focuses on the minimization of chip size. EL2 is targeted to replace sequential logic and state machines in controller SoCs. In terms of technical configuration, the EL2 is a 32-bit in-order core processor. It features a one-way scalar design and four-stage pipeline. The company informed that they expect the core to be 0.023 mm large. With this small design package, it is expected to deliver the performance characteristics of up to 3.6 CoreMarks per MHz.

Works on OmniXtend protocol

Both of the cores feature WD’s OmniXtend. Omniextend is an open cache coherence protocol utilizing the programmability of modern Ethernet switches. It enables processors, caches, memory controllers and accelerators to exchange coherence messages directly over an Ethernet-compatible fabric. It is a truly open solution for efficiently attaching persistent memory to processors. With this solution, the protocol offers potential support of advance fabrics connecting compute, storage, memory and I/O components.

Runs an open-source RISC-V software

In order to work, RISC-V needs a complete software ecosystem surrounding. The components of the ecosystem are very diverse. They are spread across all layers from low-level firmware up to fully functional kernel and applications. Each of these components is important to ensure the success of RISC-V.

Free reference design available

The company has also released its source code of register-transfer level (RTL) design abstraction. This code is available for free at GitHub. In addition, the company has also introduced the first hardware reference design for OmniXtend cache coherent memory over Ethernet protocol and transferred management and support of the architecture to Chips Alliance.

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All these design files and open source tools will help in the development of RISC  based ecosystems for high-end processors.

 


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