IAR Systems’ RISC-V-Based Embedded Workbench With Improved Development Tools

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The update includes various features such as increased code performance, maintaining good coding standards and timely detection of any errors

IAR Systems®, a Sweden-based software company for providing tools and services for embedded development, has announced the availability of a new version of the toolchain IAR Embedded Workbench® for RISC-V. This new version 1.11 adds support for custom extensions as well as enhances the code execution speed.

Features

IAR Embedded Workbench helps developers ensure that the application meet the required needs by optimising the on-board memory. With an increased code speed, version 1.11 significantly increases the performance of the executed code. To maintain good coding standards, the toolchain includes C-STAT® for integrated static code analysis. C-STAT checks compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012. It also detects any defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.

Benefits

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Using RISC-V brings flexibility which enables OEMs as well as SoC vendors to design custom cores with exact definitions as needed for the application or product. By adding support for custom extensions, embedded system designers can make full use of the capabilities of the leading embedded development toolchain.

“By using IAR Embedded Workbench for developing software for custom RISC-V cores, designers gain full flexibility for innovation and differentiation without compromising code quality or performance,” comments Anders Holmberg, Chief Strategy Officer, IAR Systems. “Our current users of the toolchain report major performance improvements compared to other RISC-V tools. OEMs that are exploring using a RISC-V core for their next embedded project can feel confident that we are delivering best in class optimizations for size and speed, as well as the support they need to keep project deadlines,” he concludes.

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RISC-V is a free and open instruction set architecture (ISA) based on established Reduced Instruction Set Computing (RISC) principles.

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