Industry’s First Terabit-Scale Ethernet PHY Enables Highest-Density

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META-DX1 uniquely combines 100 GbE, 400 GbE, FlexE, nanosecond timestamping accuracy and MACsec security engine in a single chip with terabit capacity

As cloud and telecom service providers build out their networks, they need routing and switching platforms that enable them to reduce costs, optimize bandwidth and increase capacity, security and flexibility. Microchip Technology, via its Microsemi subsidiary, is the first to enable this unique set of capabilities with its META-DX1 family of Ethernet Physical-Layer (PHY) devices that integrates, onto a single chip, Ethernet ports from 1 Gigabit Ethernet (GbE) to 400 GbE, flexible Ethernet (FlexE), Media Access Control Security (MACsec) link encryption and nanosecond timestamping accuracy at terabit capacity.

The industry is transitioning from 100 Gigabit Ethernet (GbE) to 400 GbE to support traffic within hyperscale data centers. According to Cisco’s Global Cloud Index, this traffic will quadruple by 2021 with data center to data center traffic growing at more than a 30 percent Cumulative Annual Growth Rate (CAGR). The META-DX1 enables line cards to quadruple in capacity – from 3.6 terabits per second (Tbps) to 14.4 Tbps with 36 ports of 400 GbE or 144 ports of 100 GbE – while supporting key features needed by service providers.

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The META-DX1 MACsec engine secures traffic leaving the data center or enterprise premises, and FlexE enables both cloud and telecom service providers to meet capacity requirements while reducing fiber plant capital expenditures by optimally configuring links beyond today’s fixed-rate Ethernet so they can use low-cost, high-volume optics. The META-DX1 family uniquely combines MACsec and FlexE into one solution to meet the next phase of capacity scaling in data center interconnect (DCI) buildouts. Further differentiating META-DX1, its integrated flexible crosspoint switching capability makes it easier for OEMs to navigate the market transition from 25 Gbps NRZ and 56 Gbps PAM-based architectures by enabling them to support a single design or SKU for both 100 GbE (QSFP28) and 400 GbE (QSFP-DD) optics. By providing high-performance timestamping with nanosecond-level accuracy on every port, META-DX1 also ensures network buildouts will meet the challenging timing requirements of 5G mobile base station deployments.

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Availability

Initial META-DX1 family members will sample during the third calendar quarter of 2019. All are hardware-compatible and supported by the same Software Developer’s Kit (SDK).

For additional information visit the META-DX1 webpage .

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