IAR Systems and SiFive partner to meet customers’ demands for professional solutions for RISC-V
The RISC-V technology and ecosystem are evolving rapidly. With the rapid growth, the need for professional development tools is increasing. In pursuit of this, IAR Systems and SiFive have partnered to bring IAR Systems’ compiler and debugger technology to users of SiFive’s RISC-V core IP. The companies said this partnership will offer increased possibilities for powerful RISC-V implementations with maximized performance and minimized code size.
IAR Systems, SiFive further RISC-V code optimization
SiFive offers a platform for rapidly designing, testing and building RISC‑V-based core IP and chips, to accelerate the pace of innovation for large and small businesses.
“IAR Systems, the provider of the mostly widely used toolchain for building embedded applications, now brings its expertise in compiler and debugger technology to RISC-V, providing new possibilities for maximized performance and minimized code size”, the announcement stated.
“We are dedicated to help our customers find the right solution for their specific needs,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “SiFive is a leader in commercial RISC-V core IP, and our toolchain IAR Embedded Workbench is the most widely used toolchain for building embedded applications. Together, we can help companies to boost their productivity and focus on innovation.”
“Modern compute workloads is creating Embedded Intelligence everywhere, with significant innovation at the hardware-software interface,” comments Jack Kang, VP Product Marketing, SiFive. “In order to stay ahead, companies need scalable, efficient custom silicon solutions and powerful development tools. We are excited to join forces with IAR Systems to provide new possibilities for the RISC-V community.”
IAR Embedded Workbench for RISC-V will be available mid-2019. The company claimed the toolchain will offer leading code quality, size and speed, as well as extensive, debug functionality with a fully integrated debugger with simulator and hardware debugging support.
The significant development milestones are being showcased at the SiFive booth (#202) at the RISC-V Summit on December 4th and 5th.
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