Partnership to Provide Powerful RISC-V Solutions

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Support for Andes RISC-V cores will be provided in IAR Embedded Workbench, to reduce time to market and ensure high-quality applications based on RISC-V 

IAR Systems and Andes have announced a partnership to deliver powerful development tools for Andes’ RISC-V-based solutions.

IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench.

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Andes provides the RISC-V cores, AndesCore N25(F)/NX25(F) and A25/AX25, with AndeStar V5 instruction extension and leading Andes Custom Extension (ACE) instruction customization capabilities.

A range of smart emerging applications for RISC-V

The AndesCore families are being used for a wide range of smart emerging applications including satellite navigation, high-precision sensor fusion, advanced smart meters, smart wireless communication, networking, voice processing, ADAS, storage, and machine/deep learning.

“Support for Ande’s cores in IAR Embedded Workbench will further boost the performance in these applications and ensure code density”, according to the companies.

“Andes is moving heavily into RISC-V, and we are determined to support their efforts,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “By providing maximized code speed and minimized code size for Andes powerful RISC-V cores, we will create new possibilities to reduce time to market and ensure high-quality applications based on Andes’ RISC-V ISA.”

“We are excited to partner with IAR Systems to bring new capabilities to the RISC-V community,” comments Dr. Charlie Su, CTO and Senior VP, Andes Technology Corporation. “Together, we will offer powerful solutions for Andes V5 extended ISA as well as ACE that will enable our customers to meet the demanding requirements of today’s electronic devices.”

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IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench. The toolchain offers leading code performance for size and speed, as well as extensive debug functionality with a fully integrated debugger with simulator and hardware debugging support, the announcement mentioned.

Availability

Support for Andes cores will be provided in IAR Embedded Workbench for RISC-V. The toolchain is currently under development and the first version will be available in mid-2019.

For more information, click here.

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