TSN IP Core Simplifies Design of Chips with Real-time Ethernet


A new TSN IP Core from Fraunhofer Institute for Photonic Microsystems (IPMS) will help producers and operators of manufacturing and process automation equipment who aim to extend their network devices to meet Time-Sensitive Networking (TSN) standards

Time-Sensitive Networking (TSN) is a set of standards allowing for the timed and prioritized transmission of real-time critical messages over standard Ethernet hardware. With the new TSN IP Core, developers at Fraunhofer IPMS provide equipment manufacturers and operators the opportunity to make their devices fit for new TSN standards.

Fraunhofer IPMS will be presenting the possibilities of the TSN IP Core to members of the specialist public in Hall 7a, Booth 246 at this year’s SPS IPC Drives event from 27-29 November in Nuremberg.

Background behind the development


Already a reality in many companies, intelligent Industry 4.0 automation systems connect increasingly more sensors, machines, and control units with each other. These systems must not only handle ever larger amounts of data, but especially in case of control systems and sensors/actuators, must transmit data with precise timing – often in real time. Many manufacturers of industrial devices, therefore, are currently in the process of making their devices TSN-capable.

Because Ethernet network technology typically found throughout industrial automation is not designed for difficult real-time transmission due to latencies and non-deterministic delays in overload situations, Fraunhofer IPMS provides companies support with a so-called IP Core, the announcement stated.

Dr. Frank Deicke, Head of the Fraunhofer IPMS Research Group, states, “Ethernet TSN is advantageous in that it allows data packets with real-time requirements to be prioritized ahead of less time-critical messages, and time-controlled and deterministically transmitted over standard Ethernet hardware throughout widely ramified networks. Vendor-specific real-time field buses that require specialized hardware support, that are not compliant with IEEE 802.1 and 802.3 standards, and that often interfere with each other are therefore unnecessary.”

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The Fraunhofer IPMS TSN IP CORE includes hardware modules for time synchronization (IEEE 802.1AS) and data stream management (Traffic Shaping) according to IEEE 802.1 Qav and 802.1Qbv standards as well as a dedicated Ethernet MAC for low latency. Available as a synthesizable source code or a netlist, the IP Core uses standard AMBA or Avalon interfaces to facilitate integration with your own circuits and FPGA solutions.

At the international SPS IPC Drives trade fair for intelligent automation being held from 27-29 November 2018 in Nuremberg, Fraunhofer IPMS developers will present the TSN IP Core together with industrial-grade solutions as well as customer evaluation kits for wireless optical data transmission (Li-Fi) for smaller and larger ranges. Applications of the maintenance-free and battery-less RFID Sensor Transponder will also be demonstrated.

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