The Symposium, hosted by SiFive and Open-Silicon, aimed to spread awareness about RISC-V, an open instruction set architecture that will benefit semiconductor designers at large.
SiFive, a US-based fabless semiconductor company, and Open-Silicon, a semiconductor solutions enterprise that is now part of SiFive, concluded their six city RISC-V Tech Symposium Tour in New Delhi on the 31st of August, 2018. The Symposiums started in Hyderabad and were also conducted in Bangalore, Chennai, Pune and Kolkata.
The event was attended by academic leaders and dignitaries such as Naresh Rana, Manager of Business Development, Western Digital; Pankaj Kakkar, Solutions Group Director, Cadence; Smruti Ranjan Sarangi, Associate Professor, CSE, IIT Delhi; Kunal Ghosh, Director & Co-Founder and Anagha Ghosh, Business Head & Co-Founder, VSD. The SiFive team was represented by Swamy Irrinki, Sr. Director of Marketing, Dr. Shafy Eltoukhy, SVP of Operations and GM of SoC Division, and Huzefa Cutlerywala, MD of Open-Silicon India.
Popularising RISC-V among designers
The event was hosted to spread awareness for RISC-V. RISC-V is an open instruction set architecture (ISA) that allows chip designers to create, customise and manufacture their own chips and software using the ISA freely. Despite being a new ISA, the RISC-V platform provides a large selection of open-sourced CPU designs, multiple open source OS support like Linux, FreeBSD and NetBSD and an array of software tools as well. Apart from the limited and clean instruction set provided by default, users can create their own instructions and choose to keep them private or public as they desire, provided due permissions are granted by RISC-V members.
Shafy Eltoukhy, SVP of Operations and GM of SoC Division, SiFive, said, “The fact that this open architecture has the capacity to bring custom silicon to all inventors and makers will benefit the entire semiconductor ecosystem.”
The RISC-V community is expanding with big global names like Google, NVidia, Microsemi, Western Digital among many others as well as Indian institutes like IIT-Madras and CDAC becoming members.
The event at a glance
The tech symposium in New Delhi enabled industry experts, students and engineers to share their thoughts on RISC-V ecosystem and understand the role of RISC-V to develop indigenous processors for control and security by national Government, and current research being conducted at Indian educational institutes and research organizations. The esteemed speakers used the platform to discuss the nuances of Hardware Designing and Designing complex RISC -V SoCs.
The six-city tour saw around 1250+ attendees including industry experts, engineers, researchers as well as students gather and share the platform with the esteemed speakers. During the tour, SiFive also announced first of its kind Design Contest in India, which aims to enable some of the most underutilized ideas from Indian non-commercial entities, including academic institutions, students, research groups, non-profits or individuals. SiFive will collaborate with the best ideas and provide the winners’ access to custom CPU IP, design support, and help delivering working samples for the chip. The contest will run from 21st August till 30th November 2018.