RISC-V is an open source instruction set architecture which is now being more widely adopted. Therefore, the need for a rich standardized ecosystem around deployment and debug is becoming a necessity.
UltraSoC is a member of the RISC-V Foundation that is supporting the growth of the surrounding development ecosystem. In January, the company announced the general availability of its RISC-V processor trace solution in an effort to make RISC-V adoption even easier.
Processor trace functionality is a key function for software developers using any processor. This functionality allows the behavior of a program to be viewed in detail, instruction-by-instruction.
RISC-V trace and debug solution adopted by new processor vendor
Recently, UltraSoC announced that processor intellectual property (IP) supplier Andes Technology has adopted the company’s advanced embedded analytics technology for use in its AndesCore range of RISC-V processors. Andes will leverage UltraSoC’s unique IP offering, including the commercial RISC-V processor trace solution, to accelerate development and enhance debugging of embedded products. Applications include Artificial Intelligence (AI), computer vision, network controllers, and storage.
Andes’ cores are based on the AndeStar V5 32-bit and 64-bit architectures.
“The partnership with UltraSoC allows customers for Andes V5 N25 and NX25 processors to have advanced embedded analytics capabilities integrated as an option. Customers using Andes’ high-performance 32 and 64-bit processor cores gain access to UltraSoC’s SoC analytics and debug IP in addition to RISC-V processor trace, which together give designers full visibility not only of the performance of the core but into the operation of the entire system”, the company said in the announcement.
The 32-bit N25 and the 64-bit NX25 are reported to deliver in excess of 3.4 CoreMark/MHz, with gate counts as small as 30K (N25) and 50K (NX25), and a maximum clock rate of 1.1 GHz when using TSMC’s 28nm HPC process.
The N25 and NX25 are both ideal for high-speed control tasks, and customers choosing either core will benefit from access to UltraSoC’s embedded intelligence.
The two companies plan to demonstrate a complete RISC-V development, debug, and trace flow at the upcoming RISC-V Workshop (May 7 – 10), Universitat Poletècnica de Catalunya, Spain).