RISC-V embedded processor IP provider Codasip has recently launched the 7th generation of its Studio IP-design and customization software, with significant new functionality and features. The software allows for fast configuration and optimization of RISC-V processors, customer-proprietary processor architectures, and their accompanying software development toolchains.
Studio 7 can be used for processor prototyping for a specific application domain, fast design space exploration, and development of custom extensions using Codasip’s architecture description CodAL language.
Studio then generates hardware and corresponding SDKs that are aware of the custom extensions, including:
- Verilog or VHDL RTL and System Verilog UVM environments
- testbenches and synthesis scripts
- full compiler toolchain including advanced profiling and debugging tools
- both cycle-accurate and fast instruction-accurate simulation tools
Some of the new features included in Studio 7:
- Native support for industry-standard AMBA interfaces, allowing for easy replacement of other processor cores while reusing your existing, proven peripheral IP.
- IEEE 1149-7-compatible 2-wire JTAG to minimize pin-count.
- Improvements in clock-gating for low-power requirements.
- Major updates to Codespace, the optional Eclipse-based IDE, and the underlying software tools, including support for LLVM 5.0.
“Studio 7 is a big step forward for Codasip’s advanced processor creation technology, and will take the guesswork out of implementing the ever-expanding number of ISA options in the RISC-V specification. Studio can help generate processors well-suited to the widest range of application areas, from machine learning inference engines to host processor DSP offload, networking, and storage,”stated Karel Masarik, CEO and co-founder of Codasip. “With Studio 7, there is no need to settle for a one-size-fits-all processor.”
More information: www.codasip.com