Japanese chip manufacturer Mie Fujitsu Semiconductor and Swiss research institute CSEM are collaborating on Deeply Depleted Channel (DDC) technology and near/sub-threshold voltage technology to enable low-voltage, low-power chips for the Internet of Things (IoT) and wearables markets.
Wearable and IoT devices require high energy efficiency while keeping long-battery life and small sizes. Low voltage operation is the best hope to minimize power consumption in these devices since power consumption of digital circuits is proportional to the square of the supply voltage.
To achieve this, MIFS and CSEM plan to develop an Extreme-Low Power platform using MIFS’ DDC technology which is expected to outperform conventional CMOS technologies which are reaching their limits. DDC helps the fabrication of extremely-low-leakage transistors operating at supply voltages (Vdd) below 0.5V to obtain maximum power efficiency, the Press release states.
According to the agreement, MIFS and CSEM will develop ultra-low voltage, ultra-low power standard cell libraries, power management cells and memories as well as the development of a representative qualification vehicle to showcase the technology, and will include cross-licensing of related IP.
“MIFS DDC technology offers best-in-class low voltage and low leakage operation. By working with CSEM we will be able to develop an ecosystem to make the benefits of this technology available widely to our partners”, says Masahiro Chijiiwa, Director of MIFS and Corporate Senior VP.
The new platform is expected to be available for limited release by the end of 2016.
For further details, view the full Press release.