Cadence will showcase its latest Sigrity signal analysis and power integrity technologies for system-level, power-aware multi-gigabit interface compliance at DesignCon.
The company will also demonstrate the latest multi-link and multi-protocol PHY for PCI Express (PCIe) 4.0 to address the requirements of the datacenter, server and storage markets. This next-generation PHY provides the flexibility of mixing networking protocols with a single macro and offers high-power efficiency for green datacenters.
The following technologies are scheduled for demonstration:-
• Constraint-driven power integrity design and analysis
• Power-aware memory interface design and analysis of the latest DDR and LPDDR interfaces
• Multi-gigabit serial link design and analysis
• PCIe 4.0 multi-link and multi-protocol PHY
In addition, various speaker sessions will take place to discuss new developments in these technologies and how they can help solve today’s signal integrity challenges. The sessions are planned as follows:-
• Reducing Noise in Power Distribution Networks
• Access to 3D Electromagnetic (EM) Simulation
• Learn How to Turn Simulation into Reality for PAM4 Analysis
• Needs and Capabilities for Modeling of Capacitor Derating
• Novel Power Integrity (PI) Flow Driven Using Powertree for Easier Data Visualization and Automation
• Block-Level Modeling-Based Power and Signal Integrity Performance Optimization of Integrated Core and Memory System
• Target Impedance and Rogue Waves