Low-power Floating Point Processor For M2M

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Cortus introduced a processor that offers hardware support for floating-point code. Adding to the company’s version 2 architecture, the FPS26 is aimed at embedded systems that require good floating point computational performance while also delivering small silicon area and low power dissipation.

“With version 2, we wanted to offer a range and tradeoff in computational performance. With the FPS26 we are offering a core that’s bigger than the ones we offered previously, extending our range upwards”, said Roddy Urquhart, vice president of sales and marketing at Cortus.

The CPU starts at around 0.192 mm2 using a 90nm technology. Using the Linpack benchmark, the new CPU delivers almost ten times better performance on floating-point code. The processor has a Harvard architecture, sixteen 32bit registers and a five-stage pipeline. It offers an IEEE 754 single precision hardware floating point unit, a pipelined parallel multiplier and a hardware divider. It supports the AXI4-Lite bus as well as Cortus APS peripherals.

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“The motivation for developing the FPS26 is certain use-cases for embedded systems or connected intelligent devices. Where you’ve got control systems that benefit from using floating point or where the algorithms suffer from scaling and dynamic range issues. Many motor control and power control systems tend to work better with floating point than with integer where they can face problems with insufficient word length, resulting in underflow or overflow. We are also seeing interest in floating point in wireless applications, particularly in multi-antenna MIMO systems, which have algorithms that require matrix inversions. You can have scaling issues that are easier to deal with if you have floating-point support”, added Urquhart.

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Compatible with the IEEE 754 standard, the floating-point unit performs operations such as addition, subtraction, multiplication and format conversion in hardware with less commonly used operations using software emulation based on code generated by the compiler. C code that uses floating-point datatypes will run on any of the cores in the family, with the compiler generating either hardware floating-point instructions or integer-based emulations depends on which core is the target.

Up to eight co-processors can be added to an FPS26 core. The Cortus coprocessor interface allows licensees to add custom coprocessors, for example to accelerate computations in cryptography or signal processing, without knowing details of the internals of the core. Co-processor instructions can be inserted into C-code appearing as function calls.

All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.

The APS tool chain and IDE (for C and C++) is available to licensees free of charge, and can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII, Micrium μC/OSIII & TargetOS.

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