Systems Designers can now create functional safety applications with high diagnostic coverage, compliant with safety tandards, using the Functional Safety Lockstep solution recently announced by Altera Corporation. The lockstep solution for the Nios II embedded processor reduces risk in design cycles and helps system designers simplify certification for industrial and automotive safety applications.
The joint lockstep solution uses Altera’s FPGAs, SoCs and certified tool flows, along with intellectual property (IP) cores from YOGITECH. The resultant solution enables customers to easily implement SIL3 safety designs in Altera FPGAs, including the low-cost Cyclone V FPGA and MAX 10 FPGA families.
The lockstep solution leverages YOGITECH’s industry-leading fRSmartComp technology to provide high diagnostic coverage, self-checking and advanced diagnostic features for safety-related integrated circuits, in full compliance with functional safety standards IEC 61508 and ISO 26262. The fRSmartComp technology, which is used in conjunction with Altera’s flexible Nios II embedded processors, provides diagnostic coverage greater than 99 percent without the need for difficult-to-develop ad hoc tests, speeding time-to-market.
“Developing systems based on products that already comply with the stringent safety requirements and standards required for industrial applications makes our customers’ design challenges easier,” said Roger May, system architect and functional safety lead at Altera. “This lockstep solution enables designers to take advantage of the flexibility of the already-certified Nios II processor to quickly bring their solution to market while meeting strict safety requirements, reducing risk in design cycles.”
“Thanks to the detection, self-checking and diagnostic features provided by our proven fRSmartComp technology, system developers can meet safety standards and increase availability,” said Silvano Motto, CEO of YOGITECH. “The IP is delivered with the documentation required to comply with functional safety standards, speeding time-to-market for designers and consequently reducing costs. I am very proud to announce our fRSmartComp solution is now available to Altera FPGA users.”
The solution is being demonstrated at the SPS IPC Drives conference in Nuremberg, Germany, from November 24 to 26 at the Altera stand (Hall 3, Stand #270).