Recently Silicon Storage Technology (SST), a subsidiary of Microchip has announced the launch of a 55nm embedded SuperFlash non-volatile memory (NVM) designed for secure ID, mixed-signal, NFC/RF and next-generation IoT applications.
Referring to technical documents, SuperFlash is SST’s patented and proprietary NOR flash technology. SuperFlash technology and memory cell have a number of distinct advantages for designing and manufacturing NOR flash devices, or for embedding SuperFlash memory in logic process. SuperFlash technology is fully CMOS compatible and it does not impact any logic devices. According to SST, SuperFlash technology is based on a proprietary split-gate flash memory cell which provides a cost-effective and high-performance programmable SoC solution. The SuperFlash split-gate memory cell reliably maintains its fundamental structures and operation conditions within its simple array architecture delivering service robustly for 20 years.
Referring to GLOBALFOUNDRIES, the 55nm platforms are ideal for mixed-signal and RF applications with flexible mixed-technology options for RF, eFlash, high-voltage and automotive. Available technologies include logic, analog/mixed-signal, RF, high voltage and eFlash/OTP/SRAM memory. They are design-ready solutions with silicon-validated IP and process design kits (PDK) from GLOBALFOUNDRIES and leading EDA and IP partners.
Mark Reiten, vice president of Technology Licensing for SST, a wholly owned subsidiary of Microchip said, “Embedded SuperFlash memory is a de-facto standard at foundries for microcontrollers, smartcards and various system-on-chip devices. GLOBALFOUNDRIES has been a great partner for building a state-of-the-art 55nm embedded SuperFlash platform, and we are already engaged with several customers in various market segments. We are pleased to partner with GLOBALFOUNDRIES, to further strengthen our market leadership in embedded Flash-based devices.”
Advantages offered using a SuperFlash technology:
- Fast Time to Market: SuperFlash technology is production proven with SST’s NOR flashes products before it is installed at a foundry or IDM, so it is a low risk and fast time to production for embedded applications.
- Low Power Solution:
- Low-Power Programming: SuperFlash uses source side injection for programming which is very efficient (1E-03) hence lower power than other options. Typical program current per cell is only in the range of few uA.
- Low Power for Erase Operations: SuperFlash uses FN tunnelling for Erase which is inherently very efficient hence low power. Typical Erase current per cell is in the range of tens of pA.
- Low Power Read Operation: No charge pump is needed for the Read Operation, so read power is much lower (CV2 relationship) than traditional stacked gate solutions.
- High Reliability and No SILC: Stress Induced Leakage Current is eliminated because the erase of program operations are decoupled in the cell, which also means parts can be screened for Endurance. SuperFlash uses thick tunnel oxide and an optimized scheme for Erase operation; therefore it doesn’t suffer from traditional Stress Induced Leakage Current (SILC) issues.
- Area and Performance Trade-offs: SuperFlash technology is very flexible and a solution can be optimised for either small area or high-speed read operation (100MHz).