New Multi-Core Microcontrollers For Safe Driving


Automotive security now extends to the hardware security module (HSM) system, targeting EVITA (E-safety Vehicle Intrusion Protected Applications) medium Class, which can be seen as an autonomous and isolated system, embedded into the fault tolerant microcontroller, handling all security operations. The new multi-core microcontroller from ST is designed to achieve security and make cars safe for driving.

ST has announced launch of the first device of the new SPC58NExx family of 32-bit Flash Automotive MCUs offering hardware based solution, as the company claims. According to the media release, the MCU is based on ST’s Power Architecture that combines multiple high-performance dual-issue cores with up to 6MB Flash and 768kB internal RAM memory, eight CAN (Controller Area Network) interfaces, and an optimised peripheral set based on the end application. Featuring the advantage of the multi core MCU the release states, “The multiple cores ensure redundancy in these most-important applications to meet the safety and security demands of vehicle manufacturers—and consumers.”



According to ST, the SPC58NE product line is currently available in BGA 292 and LQFP176 packaged configurations while KGD versions are also planned in the near future. The company also mentions that the launched multi-core MCU is currently under sampling for testing compliance with the ISO 26262 ASIL-D and EVITA Medium class.

Key features and specification of MCU:

  • Two 32-bit Power Architecture VLE compliant CPU core (e200z4d), dual issue, one of them being paired in lockstep
  • One 32-bit Power Architecture®VLE compliant CPU core (e200z4d), dual issue, paired in lockstep
  • 6320 kB on-chip flash memory
    • Supporting EEPROM emulation (256 kB)
    • Two Flash Controller supporting true Read-While-Read Flash access (RWR)
  • 608kB on-chip general-purpose SRAM (+160 kB data RAM included in the CPUs)
  • Multi-channel direct memory access controller (eDMA) with 96 channels, paired in lock-step
  • Dual phase-locked loops, including one frequency-modulated
  • Hardware Security Module (HSM) to provide robust integrity checking of flash memory
  • Generic timer module (GTM)
    • Intelligent complex timer module
    • 144 channels (40 inputs/104 outputs)
    • Five programmable fine grain multi-threaded cores
    • 61 kB of dedicated SRAM
    • Hardware support for engine control, motor control and safety related applications
  • Enhanced analog-to-digital converter system
  • 10 Deserial Serial Peripheral Interface (DSPI) modules, 18 LIN and UART communication interface (LINFlexD) modules, including 2 Micro Second Bus (MSB) channels
  • Seven Modular Controller Area Network (M_CAN), all ISO CAN-FD compliant, and 1 Time-Triggered Controller Area Network (M_TTCAN)
  • Dual-channel FlexRay controller, 128 channels
  • 15 SENT, 2 PSI5, 1 PSI5-S Hardware Sensor Interfaces
  • Boot Assist Module (BAM) through UART/LIN & CAN
  • Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with partial support for 2010 standard.
  • Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
  • Three Supply Controller options
    • Dual Supply Controller, 5V or 3.3V supply voltage for I/Os, 1.2V supply voltage for core logic (eLQFP176/LFBGA292)
    • Five V or 3.3V on-chip Linear Voltage Regulator with external Ballast (LFBGA292)
    • Five V DC-DC Voltage Regulator (eLQFP176 / LFBGA292)
  • Designed for eLQFP176 0.5mm pitch, LFBGA292 0.8 mm pitch


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