New Asynchronous SRAM With On-Chip ECC


Cypress announced the launch of all new 4Mb asynchronous SRAMs with on-chip Error-Correcting Code (ECC). This new SRAMs enables them to provide the highest levels of data reliability, without the need for additional error correction chips—simplifying designs and reducing board space.

Many communication channels are subject to channel noise, and thus errors may be introduced during transmission from the source to a receiver. ECC allows detecting such errors, while error correction enables reconstruction of the original data in many cases. A hardware ECC block in Cypress’s new asynchronous SRAM family performs all error correction functions inline, without user intervention, delivering best-in-class Soft Error Rate (SER) performance of less than 0.1 FIT/Mb (one FIT is equivalent to one error per billion hours of device operation) according to the company release.

The press release states, “The Cypress 4Mb asynchronous SRAMs are available in three options—Fast, MoBL and Fast with PowerSnooze—an additional power-saving Deep Sleep mode that achieves 15uA (max) deep-sleep current for the 4Mb SRAM. Each of the options are offered in industry standard x8 and x16 configurations. The devices operate at multiple voltages (1.8V, 3V, and 5V) over -40°C to +85°C (Industrial) and -40°C to +125°C (Automotive-E) temperature ranges. The 4Mb SRAMs also include an optional error indication signal that indicates the correction of single-bit errors.”


Cypress also mentions that these devices will be available in RoHS-compliant 32-pin SOIC, 32-pin TSOP II, 36-pin SOJ, 44-pin SOJ, 44-pin TSOP II and 48-ball VFBGA packages round the world.

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