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Solution Simplifies Design & Verification Of Ultra-complex SiP Packages

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Solution Simplifies Design & Verification Of Ultra-complex SiP Packages

Advanced Semiconductor Engineering and Cadence have unified to offer a System-in-Package (SiP) EDA solution that addresses the challenges of designing and verifying Fan-Out Chip-on-Substrate (FOCoS) multi-die packages.

By deploying the SiP-id methodology, chip designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging EDA tools. The end result is a vast reduction in the time needed to design and verify ultra-complex SiP packages.

The solution consists of the SiP-id (System-in-Package – intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow.

Previously, IC packaging engineers leveraged standard EDA design tools coupled with a set of loosely defined rules to lay out their packages. However, this approach has many limitations when designing today’s advanced multi-die packages.

“To provide a more holistic approach to the design and verification of SiP and advanced fan- out packages, ASE and Cadence collaborated closely to develop a design kit, methodology, and streamlined and automated reference flow using enhanced Cadence IC packaging and verification tools, all tailored for ASE’s advanced IC package technologies”, the announcement stated.

“In a typical use case with high-pin-count dies, packaging engineers using SiP-id and the accompanying reference flow and methodology were able to reduce time from more than six hours to only 17 minutes, compared to existing tools with manual operation”, the companies claimed.

“More and more of our customers are looking at multi-die advanced-package technologies to solve their next- generation design challenges,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Advanced packaging extends Moore’s Law and plays directly into our System Design Enablement strategy, so collaborating with ASE to fulfill their vision for SiP is a natural fit for us. We expect the results of this effort to mutually benefit Cadence and ASE customers by providing a methodology optimized for SiP design.”

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SiP-id is immediately available from ASE.

More information: http://www.aseglobal.com/en/Technology/AdvancedTechnology.asp

For Press release, click here.

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