To address the increasing demand of high density storage in customer retail, mobile and data center applications, Western Digital Corp and Toshiba have launched a 3D NAND, 64-layer, 512Gb capacity memory chip with 3-bits-per-cell technology.
For the new 512-gigabit device, Toshiba deployed 64-layer stacking process to realize a 65% larger capacity per unit chip size than the 48-layer 256Gbit device, and has increased memory capacity per silicon wafer, reducing the cost per bit.
“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital. “This is a great addition to our rapidly broadening 3D NAND technology portfolio. It positions us well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and data center applications.”
Toshiba already mass produces 64-layer 256-gigabit (32-gigabytes) devices and plans to expand BiCS FLASH production.
The firm’s next milestone on its development roadmap is the industry’s largest capacity, a 1-terabyte memory with a 16-die stacked architecture in a single package. Sample shipments are planned to start in April 2017.
Sample shipments of the chip started this month, and mass production is scheduled for the second half of 2017. Get more information in the Press release.