Cadence unveiled new Allegro platform with advancements to enable faster, more predictable, shorter and more cost-effective flex and rigid-flex designs commonly used in automotive, consumer electronics, computing, communications, mobile and wearable applications.
“The Allegro 17.2-2016 portfolio features comprehensive in-design inter-layer checking technology that minimizes design-check-redesign iterations and a new dynamic concurrent team design capability that accelerates product creation time by up to 50 percent. Furthermore, utilizing material inlay fabrication techniques, these new capabilities can reduce material costs by up to 25 percent”, claims Cadence.
New capabilities of the Allegro 17.2-2016 portfolio include:
• Stack-up zone for Flex and Rigid-Flex design feature provides faster, easier definition of stack ups for rigid-flex-rigid designs and improves MCAD-ECAD co-design.
• Inter-layer checks for flex and rigid-flex that saves manual effort and ensures all rules for advance flex designs are adhered to, avoiding many design-check-redesign iterations.
• Power integrity (PI) for PCB designers addressing power delivery and IR-drop issues efficiently, eliminating time-consuming iterations with PI experts.
• Interoperable Allegro and Sigrity technologies that provide an easy to use environment, which shortens design and verification time.
• New Native 3D engine provides improved visualization and collision detection to avoid unnecessary MCAD/ECAD iterations.
New synchronous team design capability, says Cadence, can shorten design time by up to 50 percent for dense designs and increase efficiency by enabling up to five PCB designers to conduct real-time, concurrent PCB design work within the same design database, shortening time to route a dense design by up to 80 percent.
“Due to the nature of our business, flex designs are extremely critical to many of our products, specifically in the mobile and automotive space. The breadth and the depth of enhancements have the ability to significantly improve our PCB design productivity in designing for space-constrained applications,” said Greg Bodi, director of System Engineering PCB Layout, Nvidia.
For further details, view the full Press release.