Cadence presents the next-generation Virtuoso platform to address the challenges designers face with advanced-node designs, complex system-level designs and emergence of new ISO standards, enabling them to fully explore, analyze and verify designs for maximising productivity and predictability while meeting aggressive time-to-market deadlines for automotive safety, medical and Internet of Things (IoT) applications.
The Cadence Virtuoso Layout Suite supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels, while the new Virtuoso Analog Design Environment (ADE) product suite enables designers to fully explore, analyse, and verify a design against design goals so that they can maintain design intent throughout the design cycle. The suite’s key technologies include Virtuoso ADE Explorer, Virtuoso ADE Assembler and Virtuoso ADE Verifier.
Including enhancements within the Cadence Virtuoso ADE and the Cadence Virtuoso Layout Suite, the new Virtuso platform is claimed to offer designers an average of 10X performance and capacity improvement across the platform. Enhanced data handling provides up to 20X improvement in loading waveform databases in excess of 1GB and a 50X improvement in versioning and loading set-up files into the environment.
“The new Virtuoso ADE Verifier technology and the Virtuoso ADE Assembler technology run plan capability make our design teams more productive. Through our early use of the new Cadence Virtuoso ADE product suite, we’ve found that we can improve analog IP verification productivity by approximately 30 percent and reduce verification issues by one-half. Our smartphone and network chip projects should benefit from these latest capabilities”, said Yanqiu Diao, deputy general manager, Turing Processor business unit at HiSilicon Technologies Co., Ltd.
The improvements in the Virtuoso Layout Suite include improved graphics rendering performance with 10X to 100X accelerated zoom, pan, drag and draw performance on large layouts. Module Generator (ModGen) adds support for synchronous clones, which are layout elements with identical physical properties, like width and length of transistors, that the layout designer can layout once and reuse. Additionally, new structured device-level routing capabilities are anticipated to enhance routing productivity by as much as 50 per cent.
For further details, view the full Press release.