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Reference Designs For High-Speed ADC Interfacing To FPGA

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Reference Designs For High-Speed ADC Interfacing To FPGA

Nowadays, ultra-high speed ADCs are becoming more and more common in areas such as Radar and advanced imaging, radios, portable test equipment and high-definition video. To deal with these high ADC interface data rates, designers have responded with faster, low-cost and highly capable FPGAs (Field Programmable Gate Arrays) as an interface between high-speed ADCs and data processing unit. An ADC passes all data to and from the DSP processor through the FPGA, allowing maximum flexibility, including preprocessing of the data in front of the DSP. FPGA designs employ very fast I/Os and dedicated Digital Signal Processing (DSP) blocks or embedded processors to process the ADC digital data. In addition, the reconfigurability of FPGA to build new designs allows them to be adapted for building interfaces with different ADC families or data processing units.

The phrase “Gigabits at milliwatts” is the driving force for designers to use serial Low voltage differential signaling (LVDS) technique for high speed data transmission, whose benefits include fast bit rates, lower power, and better noise performance. The data bus from the ADCs can be connected to the FPGA using an I/O bank configured for LVDS inputs. Replacing the parallel CMOS (3.3V logic) which required complex IO, serial LVDS interface minimizes number of IOs, provides interleaving to interleave multiple channels onto one bus. Further, serialization serializes multiple data bits onto fewer number of data lines. The simplest capture scheme to receive data from a serial interface consists of a double data rate (DDR) logic block followed by a serial-to-parallel shift register. Most FPGAs have a DDR flip-flop and register as part of the logic library.

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Mentioned below are reference designs involving interfacing of high-performance ADCs with FPGAs from Altera, Xilinx and LatticeSemi. Take a look!

  • ADC Interface using LVDS: This ADC reference design (RD1089) shows how the LatticeECP3 or LatticeECP2 FPGA can be used to interface to a high-speed ADC device. This design incorporates ADS64XX family of ADCs from Texas Instruments and LatticeECP3 FPGA high-speed LVDS I/O. The high-performance ADS64XX ADCs use serial LVDS data outputs to reduce the number of interface signals required. The design supports 12-bit, 14-bit and 16-bit ADC sample data widths, and 1-wire (one LVDS pair) and 2-wire (two LVDS pairs) interfaces. This design receives data samples input via either one or two high-speed LVDS signals and converts the serial data to parallel word format. More on this Reference Design
  • Serial LVDS High-Speed ADC Interface: This reference design illustrates a basic LVDS interface connecting a Kintex-7 FPGA to an ADC with high-speed, serial LVDS outputs. The design utilizes dedicated SelectIO technology deserializer components (ISERDESE2 primitives) in 7 series FPGAs to interface with analog-to-digital converters (ADC) with serial, low-voltage, differential signalling (LVDS) outputs. More on this Reference Design
  • ADC Interface over USB: This reference design is intended to provide the ADC interface over USB interface. The reference design board has Analog GPIO headers directly connected to Altera MAX10 FPGA. The design uses the SLS USB 2.0 Device IP Core and Altera’s ADC interface IP Core. The board interface provides the option to select ADC channels to display the analog input signals. More on this Reference Design

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