ADI has recently unveiled its latest clock jitter attenuator for base station applications. It addresses JESD204B serial interface standard for connecting high-speed data converters and FPGAs operating in GSM and LTE base station designs. The JESD204B specification describes serial data interface and the link protocol between data converters and logic devices.
According to product specification, “The HMC7044is a high performance dual-loop integer N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high-speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5GHz and 3GHz, respectively.”
In addition to this, the HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs). The DCLK and SYSREF clock outputs of the HMC7044 can be configured to support signaling standards, such as CML, LVDS,LVPECL,and LVCMOS and different bias settings to offset varying board insertion losses.
As mentioned in the release, the device costs is priced at US$ 12.75 which is available in a 10mm × 10mm LFCSP package.
HMC7044 clock jitter attenuator key features:
- JEDEC JESD204B support
- Ultra-low RMS jitter: 50fs (12 KHz to 20 MHz, typical)
- Noise floor: -162 dBc/Hz at 245.76 MHz
- Low phase noise: < -142 dBc/Hz at 800kHz to 983.04MHz output frequency
- Up to 14 device differential device clocks from PLL2
- External VCO input supports up to 5GHz
- On-board regulators for excellent PSRR